Contributions to DIPAC 2009 related to Beam Loss Monitoring
TUPB31 Configuration and Validation of the LHC Beam Loss Monitoring System
C. Zamantzas, B. Dehning, J. Emery, J. Fitzek, F. Follin, S. Jackson, V. Kain, G. Kruk, M. Misiowiec, C. Roderick, M. Sapinski
The LHC Beam Loss Monitoring (BLM) system is one of the most complex
instrumentation systems deployed in the LHC. As well as protecting the machine,
the system is also used as a means of diagnosing machine faults, and providing
feedback of losses to the control room and several systems such as the
Collimation, the Beam Dump and the Post-Mortem. The system has to transmit and
process signals from over 4'000 monitors, and has approaching 3 million
configurable parameters. This paper describes the types of configuration data
needed, the means used to store and deploy all the parameters in such a
distributed system and how operators are able to alter the operating parameters
of the system, particularly with regard to the loss threshold values. The
various security mechanisms put in place, both at the hardware and software
level, to avoid accidental or malicious modification of these BLM parameters are
also shown for each case.
paper: [pdf], poster: [pdf,
pptx]
TUPB32 Design Specifications for a Radiation
Tolerant Beam Loss Measurement ASIC
G. G. Venturini, B. Dehning,
E. Effinger, C. Zamantzas
A novel radiation hardened current digitizer ASIC is in planning stage,
aimed at the acquisition of the current signal from the ionization chambers
employed in the Beam Loss Monitoring system in CERN accelerator chain. The
purpose is to match and exceed the performances of the existing discrete
component design, currently in operation in the Large Hadron Collider (LHC). The
specifications include: a dynamic range of nine decades, defaulting to the
1pA-1mA range but adjustable by the user, ability to withstand a total
integrated dose of at least 10 kGray in 20 years of operation and user
selectable integrating windows, as low as 500ns. Moreover, the integrated
circuit can be employed to digitize currents of both polarity with a minimum
number of external components and without needing any configuration. The target
technology is IBM 130 nm CMOS process. The specifications, the architecture
choices and the reasons on which they're based upon are discussed in the paper.
paper: [pdf], poster: [pdf]
TUPB33 Systematic Study of Acquisition Electronics
with a High Dynamic Range for a Beam Loss Measurement System
G. G. Venturini, B. Dehning,
E. Effinger, J. Emery, C. Zamantzas
A discrete components design of a current digitizer based on the
current-to-frequency converter (CFC) principle is currently under development at
CERN. The design targets at rather high input current compared to similar
designs, with a maximum equal to 200mA and a minimum of 1nA, as required by the
ionization chamber that will be employed in the Proton Synchrotron and Booster
accelerators as well as in the LINAC. It allows the acquisition of currents of
both polarities without requiring any configuration and provides fractional
counts through an ADC to increase the resolution. Several architectural choices
are being considered for the front-end circuit, including charge balance
integrators, dual-integrator input stages, integrators with
switchable-capacitor, in both synchronous and asynchronous versions. The signal
is processed by an FPGA and transmitted over a VME64x bus. Design, simulations
and measurements are discussed in this article.
paper: [pdf], poster: [pdf]
TUPD26 LHC BLM Single Channel Connectivity Test
using the Standard Installation
J. Emery, B. Dehning,
E. Effinger, G. Ferioli, H. Ikeda(KEK, Ibaraki), E. Verhagen (UW-Madison/PD,
Madison, Wisconsin), C. Zamantzas
For the LHC beam loss measurement system the high voltage supply of the
ionisation chambers and the secondary emission detectors is used to test their
connectivity. A harmonic modulation of 0.03 Hz results in a current signal of
about 100 pA measured by the beam loss acquisition electronics. The signal is
analyzed and the measured amplitude and phase are compared with individual
channel limits for the 4000 channels. It is foreseen to execute an automatic
procedure for all channels every 12 hours which takes about 20 minutes. The
paper will present the design of the system, the circuit simulations,
measurements of systematic dependencies of different channels and the
reproducibility of the amplitude and phase measurements.
paper: [pdf], poster: [pdf,
ppt]
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